1. Field of the Invention
The present invention relates to duty correction circuits which correct duty ratios of clock signals generated by frequency dividers adapted to digital circuits.
The present application claims priority on Japanese Patent Application No. 2008-133113, the content of which is incorporated herein by reference.
2. Description of Related Art
Conventionally, various technologies for controlling duty ratios of clock signals in synchronization with timings for transmitting signals between digital circuits have been developed and disclosed in various documents such as Patent Document 1.                Patent Document 1: Japanese Unexamined Patent Application Publication No. 2000-68797        
For example, synchronization circuits used for synchronization of circuit operations need to set duty ratios of signals in circuits to 50%.
FIG. 8 shows a timing control circuit incorporated in a duty ratio correction circuit disclosed in Patent Document 1, wherein an inverter including a P-channel MOS transistor (hereinafter, simply referred to as a PMOS transistor) MP1 and an N-channel MOS transistor (hereinafter, simply referred to as an NMOS transistor) MN1 is associated with PMOS transistors MP2 and MP3 and NMOS transistors MN2 and MN3 so as to adjust and correct the duty ratio of an input signal S6, thus outputting an output signal S10, which is controlled at the leading-edge timing, to an inverting input terminal of a comparator A1 via a capacitor C1.
In order to adjust the duty ratio of the inverter shown in FIG. 8, the PMOS transistors MP2 and MP3 are connected in parallel between the source of the PMOS transistor MP1 and the power-supply voltage VDD while the NMOS transistors MN2 and MN3 are connected in parallel between the source of the NMOS transistor MN1 and the ground GND.
A constant bias voltage VBP is supplied to the gates of the PMOS transistors MP2 and MP3, while a constant bias voltage VBN is supplied to the gate of the NMOS transistor MN2. Electric charge is accumulated in the capacitor C1 due to a constant current flowing through the PMOS transistor MP1.
A control signal S9 is supplied to the gate of the NMOS transistor MN3 so as to control the leading-edge timing. A current flowing through the NMOS transistor MN3 varies depending upon the potential of the control signal S9, thus adjusting the trailing-edge timing of the output signal S10 of the inverter. The comparator A1 compares the output signal S10 with a reference voltage Vref (supplied to the noninverting input terminal thereof), thus adjusting the duty ratio.
Due to recent trends in increasing processing speeds of semiconductor devices, i.e. due to increasing high-speed clocking, it is necessary to secure high-speed adjustment on waveforms of clock signals in short clock periods.
Even though duty correction circuits are developed to precisely adjust duty ratios to desired values in manufacturing stages of semiconductor devices, transistor characteristics may not be normally fixed to design values due to dispersions of manufacturing processes; hence, it is very difficult to adjust duty ratios to desired values.
In the above, it is necessary for manufacturers to check and revise conditions of manufacturing processes and to make transistor characteristics suit manufacturing processes, so that semiconductor devices are property re-manufactured.
The present inventors have recognized that, in the duty ratio correction circuit of FIG. 8 disclosed in Patent Document 1 in which the duty ratio of an input signal is adjusted using PMOS transistors and NMOS transistors, when NMOS transistors are re-adjusted in characteristics due to revised manufacturing processes, PMOS transistors must be correspondingly varied in characteristics in association with NMOS transistors; hence, it is very difficult to precisely adjust the duty ratio because both the PMOS transistors and NMOS transistors cannot be simultaneously subjected to high-precision controlling of characteristics thereof.